1. Field of the Invention
This invention relates to a static memory device, and more particularly to a static memory device which writes and reads data at a high speed.
2. Description of the Related Art
In a static random access memory (hereinafter referred to as a SRAM), data is transmitted from a write circuit through a bit line and written in a memory cell selected on the basis of a row selection signal output from a row decoder and a column selection signal output from a column decoder.
In a data reading operation, data is read from a memory cell selected in the same manner as described above. The data is supplied through a bit line to a sense amplifier and amplified therein. Recently, some BICMOS circuits consisting of CMOS FETs and bipolar transistors have a sense amplifier formed of bipolar transistors.
In a conventional SRAM using a CMOS FET and a bipolar transistor, the potential of a bit line is precharged to a value V.sub.BL =V.sub.cc -2V.sub.f or V.sub.cc -V.sub.f because of the use of bipolar sense amplifier, where V.sub.cc denotes a supply voltage and V.sub.f denotes a base-emitter forward bias voltage and the emitter of the bipolar transistor. Therefore, when data is written, the voltage margin to correctly write data is small and a write time is long.
When data writing and data reading are consecutively performed, the time required to read data through a pair of bit lines connected to a memory cell in which data has just been written is different from the time required to read the data through another pair of bit lines. More specifically, when the later pair of bit lines is accessed, the two bit lines are precharged to a potential of V.sub.BL (e.g., V.sub.cc -2V.sub.f), and accordingly, data can be read out in a relatively short period of time. However, when the pair of bit lines connected to the memory cell in which data has just been written is accessed again to read data from another memory cell (or the same memory cell), a relatively long period of time is required. For example, in one write cycle, one of the pair of bit lines is set at the potential of V.sub.cc -2V.sub.f and the other bit line is set at a lower level. When a data reading operation starts, it takes a considerable period of time to return the lower potential level of the pair of bit lines to the level of V.sub.BL. In addition, it requires much longer time to read data in a memory cell of a high level through a bit line which is set at a low level in previous write cycle, since the potential of the bit line must be inverted.